1. Field of the Invention
The present invention relates to a semiconductor device including a circuit composed of a thin film transistor on a substrate that has an insulating surface, and to a method of manufacturing the same. For instance, the invention relates to the construction of an electro-optical device, exemplified by a liquid crystal display device, and an electronic equipment provided with the electro-optical device. Incidentally, the semiconductor device in the present specification designates devices in general which function by utilizing semiconductor characteristic. The electro optical device and electronic equipment provided with the electro optical device mentioned above therefore fall into category of the semiconductor device.
2. Description of the Related Art
Development in application of thin film transistors (hereinafter referred to as TFT) to active matrix liquid crystal display devices has been actively proceeded, because TFT allows the use of a transparent grass substrate in fabrication. The TFT having as its active layer a semiconductor film with a crystal structure (hereinafter referred to as crystalline TFT) provides high mobility, making it possible to integrate function circuits on a single same substrate and thus realize image display of high definition.
In the present specification, the semiconductor film with a crystalline structure, mentioned above, includes a single crystalline semiconductor, a polycrystalline semiconductor and a microcrystalline semiconductor, and further includes semiconductors disclosed in Japanese Patent Application Laid-Open Nos. Hei 7-130652, Hei 8-78329, Hei 10-135468, and Hei 10-135469.
Upon construction of an active matrix liquid crystal display device, a pixel matrix circuit alone requires 1 to 2 million crystalline TFTs, and even more crystalline TFTs in total need to be contained if function circuits to be disposed at the periphery are added. Also, reliability of each of those crystalline TFTs has to be secured in order to operate stably the liquid crystal display device.
It can be said that characteristic of field effect transistors, such as TFTs, has three distinguishable domains: a linear domain where drain current and drain voltage increase in proportion to each other, a saturation domain where drain current reaches saturation even if drain voltage increases, and a cut-off domain where, ideally, current does not flow even if drain voltage is applied. In this specification, the linear domain and the saturation domain are called ON-domains of TFT, and the cut-off domain, an OFF-domain. Also, for convenience""s sake, drain current in the ON-domain is referred to as ON-current, and current in the OFF-domain as OFF-current.
The pixel matrix circuit in the active matrix liquid crystal display device is comprised of an n-channel TFT (hereinafter referred to as pixel TFT). Applied with a gate voltage of about 15 to 20 V amplitude, the TFT needs to satisfy the characteristic both in the ON-domain and the OFF-domain. On the other hand, a peripheral circuit provided to drive the pixel matrix circuit is constructed using a CMOS circuit as a base, and mainly the characteristic in the ON-domain is significant. However, the crystalline TFT has a problem in that OFF-current tends to increase. In addition, when the crystalline TFT is driven for a long period of time, degradation phenomena such as reduction in mobility and ON-current, and increase in OFF-current are often observed. One of factors of this is considered to be the hot carrier implantation phenomenon, which is caused by high electric field in the vicinity of the drain.
Lightly Doped Drain (LDD) structure is known in the LSI technical field as measure to reduce OFF-current of an MOS transistor and further to ease high electric field in the vicinity of the drain. In this structure, an impurity region with low concentration is provided between a drain region and a channel formation region, and this impurity region with low concentration is called an LDD region.
Similarly, to form the LDD structure in the crystalline TFT is known. According to the prior art, the method comprises: forming, through a first impurity element doping step, an impurity region with low concentration to be an LDD region, while using a gate electrode as a mask; forming thereafter side walls on both sides of the gate electrode, by utilizing anisotropic etching technique; and forming, through a second impurity element doping step, an impurity region with high concentration to be a source region and a drain region, while using as a mask the gate electrode and the side walls.
However, in comparison with a TFT having an ordinary structure, the LDD structure TFT may reduce OFF-current but increases series resistance component due to its makeup, resulting in undesirable decrease in ON-current of the TFT. Also, the LDD structure can not completely prevent degradation of ON-current. Known as measure to compensate these defects is the structure in which the LDD region overlaps with the gate electrode through a gate insulating film. This structure may be formed by several ways, and, for example, there are known GOLD (Gate-drain Overlapped LDD) and LATID (Large-tilt-angle implanted drain). With such structure, high electric field in the vicinity of the drain may be eased to enhance hot carrier resistance and, at the same time, decrease in ON-current can be prevented.
In the crystalline TFT also, it has been confirmed that the provision of the LDD structure improves hot carrier resistance and further adoption of the GOLD structure provides very superior effect, as compared to the crystalline TFT of a simple structure consisting of the source region, the drain region and the channel formation region (xe2x80x9cNovel Self-aligned Gate-overlapped LDD Poly-Si TFT with High Reliability and Performancexe2x80x9d Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97-523).
In the crystalline TFT, formation of the LDD structure is effective means to suppress hot carrier implantation phenomenon. When the GOLD structure is further employed, decrease in ON-current observed in the LDD structure can be prevented. Those structures provide good results also in terms of reliability.
Thus, structural examination of the element is required to achieve high reliability for the crystalline TFT, and formation of the GOLD structure is desirable for that point. In conventional methods, however, the LDD region may be formed in a self-alignment manner but the step of forming a side wall film by anisotropic etching is unsuited to process a large grass substrate as in the case of the liquid crystal display device. In addition, the length of the LDD region is determined by the width of the side walls, putting high limitation on degree of freedom in designing the element.
A first object of the present invention is to provide a technique to overcome those problems, and specifically to provide, through a simpler method than in the prior art, a technique of manufacturing a crystalline TFT with the structure in which a gate electrode overlaps with an LDD-region.
Though the GOLD structure may prevent degradation of ON-current, as in particularly an n-channel TFT that constitutes a pixel matrix circuit, OFF-current is sometimes increased upon application of a high gate voltage in the OFF-domain. OFF-current increases in the pixel TFT of the pixel matrix circuit, causing inconveniences such as increase in power consumption and troubled image display. This is probably because an inversion layer is formed in the LDD region formed to overlap with the gate electrode in the OFF-domain, making a passage of a hole. In that case, operation range of the TFT is narrowed and limited.
A second object of the present invention is to provide the structure for preventing increase of OFF-current in the crystalline TFT, in which a gate electrode overlaps with an LDD region, So that the operation range of the TFT may be widened, and to provide a method of making that structure.
FIGS. 17A-1 to 17B-4 are views schematically showing structures of the TFT and Vgxe2x88x92Id (gate voltage-drain current) characteristics obtained with the structures based on the knowledge known so far. FIG. 17A-1 shows the simplest TFT structure in which a semiconductor layer consists of a channel formation region, a source region and a drain region. FIG. 17B-1 shows characteristic of this TFT, and the side +Vg in the drawing is the ON-domain of the TFT while the side xe2x88x92Vg is the OFF-domain. The solid line in the drawing represents initial characteristic while the broken line represents degradation characteristic caused by the hot carrier implantation phenomenon. In this structure, ON-current as well as OFF-current is high and a considerable degradation takes place. This structure is therefore impossible to use as it is for a pixel TFT of a pixel matrix circuit, for example.
FIG. 17A-2 shows the structure in which an impurity region with low concentration to be an LDD region is added to the structure of FIG. 17A-1. This is the LDD structure that does not overlap with the gate electrode. FIG. 17B-2 shows characteristic of this TFT, with which degradation of ON-current cannot be prevented though OFF-current may be suppressed to a certain extent. FIG. 17A-3 shows the structure in which the LDD region completely overlaps with the gate electrode, called the GOLD structure. FIG. 17B-3 shows characteristic corresponding thereto, with which degradation may be reduced down to a level causing no problem but OFF-current on the xe2x88x92Vg side is increased as compared to the structure of FIG. 17A-2.
In contrast to those, as shown in FIG. 17B-4, the structure of FIG. 17A-4 can prevent degradation and also suppress increase of OFF-current. The structure is divided into two regions: in one region, the LDD region overlaps with the gate electrode and in the other region, the LDD region does not. The structure has both effects of restricting the hot carrier implantation phenomenon in the LDD region overlapping with the gate electrode and of preventing increase of OFF-current in the LDD region not overlapping with the gate electrode.
According to the present invention, the LDD region overlaps with the gate electrode in an n-channel TFT in order to realize the TFT having the structure as in FIG. 17A-3 or FIG. 17A-4. To fulfill that purpose, the gate electrode is comprised of a first conductive layer and a second conductive layer; an impurity element for giving n-type is doped for the first time after the first conductive layer is formed, to thereby form a first impurity region to be the LDD region; and a second doping step of an impurity element for giving n-type is carried out after the second conductive layer is formed, to thereby forming a second impurity region to be a source region and a drain region. In this way, the structure in which the LDD region overlaps with the gate electrode is obtained. To further provide the LDD region that does not overlap the gate electrode, a part of the second conductive layer is removed.
On the other hand, in a p-channel TFT, a part of a third impurity region to be a source region and a drain region overlaps with a gate electrode that consists of a first conductive layer and a second conductive layer, as in the n-channel TFT.
The first conductive layer is formed from one or more kinds of elements selected from a group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or from a material containing those elements as ingredients. In a preferred mode of such a constitution, the first conductive layer comprises at least a conductive layer (A) made of the elements or material above and formed to come in contact with a gate insulating film, and a conductive layer (B) formed on the conductive layer (A) and made from either one or both of aluminum (Au) element and copper (Cu) element, or from a material containing those elements as ingredients.
The second conductive layer is formed from one or more kinds of elements selected from a group consisting of titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo), or from an alloy material containing those elements as ingredients.
In the pixel matrix circuit constitution, a holding capacitance is comprised of: a semiconductor layer disposed so as to be in contact with the second impurity region of the pixel TFT, and containing as high concentration of impurity elements as the first impurity region; an insulating layer formed of the same layer that the gate insulating film is formed of; and a capacitance wiring formed on the insulating layer. Alternatively, the holding capacitance is comprised of: a semiconductor layer disposed so as to be in contact with the second impurity region of the pixel TFT, and containing as high concentration of impurity elements as the third impurity region; an insulating layer formed of the same layer that the gate insulating film is formed of; and a capacitance wiring formed on the insulating layer.